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FPGA Implementation of an 8-bit Simple Processor using spartan-3e FPGA board

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Problem : [ ( A + B ) / 2 ] * [ ( A + B ) / 2 ]
Board: Spartan 3e
Program: Xlinix ISE

Project Steps:
Step 1: Design ALU
Step 2: Design Register
Step 3: Design Control Unit
Step 4: Design Top Module
Step 5: Design Test Module
Step 6: Similuation

 

 

Step 1: Design ALU

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Step 2: Design Register

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Step 3: Design Control Unit

Top Module

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Step 4: Design Top Module

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Step 5: Design Test Module
Step 6: Similuation

 

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Top.v

 

 

 

 

 

 

 


So, what do you think ?